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[ak5358b] ms1155-e-00 2010/02 - 1 - general description the ak5358b is a stereo a/d converter wi th a wide sampling rate range of 8khz 96khz and it is suitable for consumer to professional audio system. the ak5358b achieves high accuracy and low cost by using enhanced dual bit ? techniques. no external components ar e required with single-ended analog inputs. the audio interface has two formats (msb justified, i 2 s) and can correspond to va rious systems like dtv, dvr and av receiver. features ? linear phase digital anti-alias filtering ? single-ended input ? digital hpf for dc-offset cancel ? s/(n+d): 92db ? dr: 102db ? s/n: 102db ? sampling rate ranging from 8khz to 96khz ? master clock: 256fs/384fs/512fs/768fs (8khz 48khz) 256fs/384fs (48khz 96khz) ? input level: ttl/cmos ? master / slave mode ? audio interface: 24bit msb justified / i 2 s selectable ? power supply: 4.5 5.5v (analog), 2.7 5.5v (digital) ? ta = ? 20 85 c ? small 16pin tssop package ? ak5357/59/81/58a pin-compatible ? modulator mclk ainl lrck sclk sdto dif vcom clock divider ainr vss1 va decimation filter serial i/o interface vo l ta g e re f e re n c e cks1 vss2 vd cks 2 ? modulator decimation filter pdn cks0 96khz 24-bit ? adc ak5358b
[ak5358b] ms1155-e-00 2010/02 - 2 - ordering guide AK5358BET ? 20 +85 c 16pin tssop (0.65mm pitch) akd5358b evaluation board for ak5358b pin layout cks1 vcom vd vss2 ainr ainl vss1 va top view 8 7 6 5 4 3 2 1 9 10 11 12 13 14 15 16 dif pdn lrck mclk sclk cks2 cks0 sdto compatibility with ak5357, ak5359 and ak5381 ak5357 ak5358b ak5358a ak5381 ak5359 fs 4khz to 96khz 8khz to 96khz 8khz to 96khz 4khz to 96khz 8khz to 216khz s/(n+d) 88db 92db 92db 96db 94db dr 102db 102db 102db 106db 102db vih@ttl level mode 2.2v 2.2v 2.2v 2.4v not available va (analog supply) 2.7 to 5.5v 4.5 to 5.5v 4.5 to 5.5v 4.5 to 5.5v 4.5 to 5.5v 2.7 to 5.5v vd (digital supply) 2.7 to 5.5v 2.7 to 5.5v 2.7 to 5.5v 3.0 to 5.5v @96khz 3.0 to 5.5v hpf disable available not available not available available available operating temperature et: ? 20 +85 c vt: ? 40 +85 c et: ? 20 +85 c et: ? 20 +85 c et: ? 20 +85 c vt: ? 40 +85 c xt: ? 40 +85 c et: ? 20 +85 c vt: ? 40 +85 c mclk, lrck, bick clock stop not available available not available not available not available
[ak5358b] ms1155-e-00 2010/02 - 3 - pin / function no. pin name i/o function 1 ainr i rch analog input pin 2 ainl i lch analog input pin 3 cks1 i mode select 1 pin 4 vcom o common voltage output pin, va/2 bias voltage of adc input. 5 vss1 - ground pin 6 va - analog power supply pin, 4.5 5.5v 7 vd - digital power supply pin, 2.7 5.5v 8 vss2 - ground pin 9 sdto o audio serial data output pin ?l? output at power-down mode. 10 lrck i/o output channel clock pin ?l? output in master mode at power-down mode. 11 mclk i master clock input pin 12 sclk i/o audio serial data clock pin ?l? output in master mode at power-down mode. 13 pdn i power down mode & reset pin ?h?: power up, ?l?: power down & reset 14 dif i audio interface format pin ?h?: 24bit i 2 s compatible, ?l?: 24bit msb justified 15 cks2 i mode select 2 pin 16 cks0 i mode select 0 pin note: all input pins except analog input pins (ainr, ainl) should not be left floating. handling of unused pin the unused input pins must be processed appropriately as below. classification pin name setting ainl this pin must be open. analog ainr this pin must be open.
[ak5358b] ms1155-e-00 2010/02 - 4 - absolute maximum ratings (vss1=vss2=0v; note 1 ) parameter symbol min max units power supplies: analog digital| va vd ? 0.3 ? 0.3 6.0 6.0 v v input current, any pin except supplies iin - 10 ma analog input voltage (ainl, ainr, cks1 pins) vina ? 0.3 va+0.3 v digital input voltage ( note 2 ) vind ? 0.3 vd+0.3 v ambient temperature (powered applied) ta ? 20 85 c storage temperature tstg ? 65 150 c note 1. all voltages with respect to ground. note 2. pdn, dif, mclk, sclk, lrck, cks0, cks2 pins warning: operation at or beyond these limits may result in permanent damage to the device. normal operation is not guaranteed at these extremes. recommended operating conditions (vss1=vss2=0v; note 1 ) parameter symbol min typ max units power supplies ( note 3 ) analog digital va vd 4.5 2.7 5.0 5.0 5.5 va v v note 3. the power up sequence between va and vd is not critical. warning: akm assumes no responsibility for the us age beyond the conditions in this datasheet.
[ak5358b] ms1155-e-00 2010/02 - 5 - analog characteristics (ta=25 c; va=5.0, vd=5.0v; vss1=vss2=0v; fs=48khz, 96khz; sclk=64fs; signal frequency=1khz; 24bit data; measurement frequency=20hz 20khz at fs=48khz, 40hz 40khz at fs=96khz; unless otherwise specified) parameter min typ max units adc analog input characteristics: resolution 24 bits input voltage ( note 4 ) 2.7 3.0 3.3 vpp ? 1dbfs 82 92 db fs=48khz bw=20khz ? 60dbfs - 39 db ? 1dbfs - 90 db s/(n+d) fs=96khz bw=40khz ? 60dbfs - 38 db dr ( ? 60dbfs, a-weighted) 94 102 db s/n (a-weighted) 94 102 db fs=48khz 13 20 k input resistance fs=96khz 9 14 k interchannel isolation 90 110 db interchannel gain mismatch 0.1 0.5 db gain drift 100 - ppm/ c power supply rejection ( note 5 ) - 50 db power supplies power supply current normal operation (pdn pin = ?h?) va vd (fs=48khz) ( note 6) vd (fs=96khz) ( note 7) power down mode (pdn pin = ?l?) ( note 8) va+vd 12 3 6 10 18 5 9 100 ma ma ma a note 4. this value is the full scale (0db) of the input voltage. input voltage is proportional to va voltage. vin = 0.6 x va (vpp). note 5. psr is applied to va and vd with 1khz, 50mvpp. note 6. vd=2ma@3v note 7. vd=4ma@3v note 8. all digital input pins and cks1 pin are held vd or vss2.
[ak5358b] ms1155-e-00 2010/02 - 6 - filter characteristics (fs=48khz) (ta=-20 c 85 c; va=4.5 5.5v; vd=2.7 5.5v) parameter symbol min typ max units adc digital filter (decimation lpf): passband ( note 9) 0.1db ? 0.2db ? 3.0db pb 0 - - 20.0 23.0 18.9 - - khz khz khz stopband sb 28 khz passband ripple pr 0.04 db stopband attenuation sa 68 db group delay distortion gd 0 s group delay ( note 10 ) gd 16 1/fs adc digital filter (hpf): frequency response ( note 9 ) ? 3db ? 0.1db fr 1.0 6.5 hz hz filter characteristics (fs=96khz) (ta=-20 c 85 c; va=4.5 5.5v; vd=2.7 5.5v) parameter symbol min typ max units adc digital filter (decimation lpf): passband ( note 9) 0.1db ? 0.2db ? 3.0db pb 0 - - 40.0 46.0 37.8 - - khz khz khz stopband sb 56 khz passband ripple pr 0.04 db stopband attenuation sa 68 db group delay distortion gd 0 s group delay ( note 10 ) gd 16 1/fs adc digital filter (hpf): frequency response ( note 9) ? 3db ? 0.1db fr 2.0 13.0 hz hz note 9. the passband and stopband frequencies scale with fs. for example, pb=48khz@ 0.1db is 0.39375 fs. note 10. the calculated delay time induced by digital filtering. this time is fro m the input of an analog signal to the setting of 24bit data both channels to the adc output register for adc.
[ak5358b] ms1155-e-00 2010/02 - 7 - dc characteristics (cmos level mode) (ta=-20 c 85 c; va=4.5 5.5v; vd=2.7 5.5v; cks2/1/0 = ?lll?, ?lhl?, ?lhh?, ?hhl?, ?hhh?) parameter symbol min typ max units high-level input voltage low-level input voltage vih vil 70%vd - - - - 30%vd v v high-level output voltage (iout= ? 1ma) low-level output voltage (iout=1ma) voh vol vd ? 0.5 - - - - 0.5 v v input leakage current iin - - 10 a dc characteristics (ttl level mode) (ta=-20 c 85 c; va=4.5 5.5v; vd=4.5 5.5v; cks2/1/0 = ?hll?) parameter symbol min typ max units high-level input voltage (cks2-0 pins) (all pins except cks2-0 pins) low-level input voltage (cks2-0 pins) (all pins except cks2-0 pins) vih vih vil vil 70%vd 2.2 - - - - - - - - 30%vd 0.8 v v v v high-level output voltage (iout= ? 1ma) low-level output voltage (iout=1ma) voh vol vd ? 0.5 - - - - 0.5 v v input leakage current iin - - 10 a
[ak5358b] ms1155-e-00 2010/02 - 8 - switching characteristics (ta=-20 c 85 c; va=4.5 5.5v; vd=2.7 5.5v; c l =20pf) parameter symbol min typ max units master clock timing ( note 11 ) 512fs, 256fs frequency duty cycle 768fs, 384fs frequency duty cycle fclk dclk fclk dclk 2.048 40 3.072 40 24.576 60 36.864 60 mhz % mhz % lrck frequency fs 8 96 khz duty cycle slave mode master mode 45 50 55 % % audio interface timing slave mode sclk period sclk pulse width low pulse width high lrck edge to sclk ? ? ( note 12 ) sclk ? ? to lrck edge ( note 12 ) lrck to sdto (msb) (except i 2 s mode) sclk ? ? to sdto tsck tsckl tsckh tlrsh tshlr tlrs tssd 160 65 65 30 30 35 35 ns ns ns ns ns ns ns master mode sclk frequency sclk duty sclk ? ? to lrck sclk ? ? to sdto fsck dsck tmslr tssd ? 20 ? 20 64fs 50 20 35 hz % ns ns reset timing pdn pulse width ( note 13 ) pdn ? ? to sdto valid at slave mode ( note 14 ) pdn ? ? to sdto valid at master mode ( note 14 ) tpd tpdv tpdv 150 4132 4129 ns 1/fs 1/fs note 11. the ak5358b is reset by more than 13us ?l? pe riod of mclk. the data is output after initializing. note 12. sclk rising edge must not occur at the same time as lrck edge. note 13. the ak5358b can be reset by bringing the pdn pin = ?l?. note 14. this cycle is the number of lrck rising edges from the pdn pin = ?h?.
[ak5358b] ms1155-e-00 2010/02 - 9 - timing diagram 1/fclk mclk tclkh tclkl vih vil 1/fs lrck vih vil tsck sclk tsckh tsckl vih vil dclk=tclkh x fclk, tclkl x fclk clock timing lrck vih vil tshlr sclk vih vil tlrs sdto 50%vd tlrsh tssd audio interface timing (slave mode)
[ak5358b] ms1155-e-00 2010/02 - 10 - lrck sclk 50%vd sdto 50%vd tssd tmslr dsck 50%vd audio interface timing (master mode) tpd pdn vil pdn vih vil tpdv sdto 50%vd power down & reset timing
[ak5358b] ms1155-e-00 2010/02 - 11 - operation overview system clock mclk, sclk and lrck (fs) clocks are required in slave mode. the lrck clock input must be synchronized with mclk, however the phase is not critical. table 1 shows the relationship of typical sampling frequency and the system clock frequency. mclk frequency, sclk fre quency and master/slave modes are selected by cks2-0 pins as shown in table 2 . mclk fs 256fs 384fs 512fs 768fs 32khz 8.192mhz 12.288mhz 16.384mhz 24.576mhz 44.1khz 11.2896mhz 16.9344mhz 22.5792mhz 33.8688mhz 48khz 12.288mhz 18.432mhz 24.576mhz 36.864mhz 96khz 24.576mhz 36.864mhz n/a n/a table 1. system clock example mode cks2 cks1 cks0 input level master/slave mclk sclk 0 l l l cmos slave 256/384fs (8k fs 96k) 512/768fs (8k fs 48k) 48fs or 32fs ( note 15 ) 1 l l h reserved 2 l h l cmos master 256fs (8k fs 96k) 64fs 3 l h h cmos master 512fs (8k fs 48k) 64fs 4 h l l ttl slave 256/385fs( 96khz) 512/768fs( 48khz) 48fs or 32fs ( note 15 ) 5 h l h reserved 6 h h l cmos master 384fs (8k fs 96k) 64fs 7 h h h cmos master 768fs (8k fs 48k) 64fs table 2. operation mode select note 15. sdto outputs 16bit data at sclk=32fs.
[ak5358b] ms1155-e-00 2010/02 - 12 - audio interface format two kinds of data formats can be selected by the dif pin ( table 3 ). in both modes, the serial data is in msb first, 2?s compliment format. the sdto is clocked out on the falling e dge of sclk. the audio inte rface supports both master and slave modes. in master mode, sclk and lrck are output with the sclk frequency fixed to 64fs and the lrck frequency fixed to 1fs. mode dif pin sdto lrck sclk figure 0 l 24bit, msb justified h/l 48fs or 32fs figure 1 1 h 24bit, i 2 s compatible l/h 48fs or 32fs figure 2 table 3. audio interface format lrck sclk(64fs) sdto(o) 0 23 22 1 2 4 0 20 21 24 31 0 12 23 22 0 1 0 23 22 20 21 31 23:msb, 0:lsb lch data rch data 24 321 22 23 23 1 2 3 4 figure 1. mode 0 timing lrck sclk(64fs) sdto(o) 0 23 22 1 2 4 0 25 21 24 0 12 23 22 0 1 0 22 25 21 24 321 22 23 23 1 2 3 4 3 23:msb, 0:lsb lch data rch data figure 2. mode 1 timing digital high pass filter the adc has a digital high pass filter for dc offset cancellation. the cut-off frequency of the hpf is 1.0hz (@fs=48khz) and it scales with sampling rate (fs).
[ak5358b] ms1155-e-00 2010/02 - 13 - power down the ak5358b is placed in power-down m ode by bringing the pdn pin ?l? or mclk stop more than 13us, and the digital filter is also reset at the same time. this reset s hould always be made after powe r-up. in power-down mode, the vcom is same level as vss1. mclk and lrck must be input when the pdn pin is ?h? to release the power down mode. an analog initialization cycle starts after exiting the power-down mode. therefore, the output data sdto becomes available after 4129 cycles of lrck clock in master mode or 4132 cycles of lrck clock in slave mode. during initialization, the adc digital data outputs of both channels are forced to a 2?s complement ?0?. the adc outputs are settled in the data corresponding to the input signals afte r the end of initialization (se ttling approximately takes the same time as group delay). nor mal oper ation internal state pdn power-down initialize normal operation (1) idle noise gd gd ?0?data a /d in (analog) a /d out (di gital ) c lock in m clk,lrck,sclk (2) (3 ) (4) ?0?data idle nois e figure 3. power-down/up sequence example (pdn pin reset) normal operation internal state pdn power-down initialize normal operation (1 ) idle noise gd gd ?0?data a /d in (analog) a /d out (digital ) c lock in m clk (2) (3 ) ?0 ?d ata idle noise (5) (6) figure 4. power-down/up sequence example (mclk stop reset) notes: (1) 4132/fs in slave mode and 4129/fs in master mode. (2) digital output corresponding to analog input has the group delay (gd). (3) a/d outputs ?0? data at the power-down state. (4) mclk is input as normal operation. (5) when mclk is stopped more than 13us, the ak5358b becomes power down mode. (6) mclk and lrck must be input to release power-down mode.
[ak5358b] ms1155-e-00 2010/02 - 14 - system reset the ak5358b must be reset once by br inging the pdn pin ?l? or inputting mc lk 13us (min) after the ak5358b is powered-up. in slave mode, the internal timing starts clocking by the rising edge (falling edge at mode 1) of lrck after exiting from reset and power down state by mclk. the ak5358b is power down st ate until lrck is input. in master mode, the internal timing starts when mclk is input.
[ak5358b] ms1155-e-00 2010/02 - 15 - system design figure 5 shows the system connection diagram. an evaluation board is available which demonstrates application circuits, the optimum layout, power supply arrangements and measurement results. ak5358b 8 7 6 3 2 1 9 10 11 12 13 14 15 16 ainl vcom vss1 vss2 ainr sdto lrck mclk sclk pdn + 0.1u cks1 va vd analog 5v dif cks2 cks0 10u 10u 0.1u reset 5 4 audio controller mode control + 2.2u 10u 10u + + analog ground system ground lch in rch in digital 3.3v note: - vss1 and vss2 of the ak5358b should be distributed separately from the ground of external digital devices (mpu, dsp etc.). - all digital input pins should not be left floating. - the cks1 pin should be connected to va or vss1. figure 5. typical connection diagram analog ground digital ground system controller a inr 1 a inl 2 cks1 3 vcom 4 vss1 5 va 6 vd 7 vss2 8 16 15 14 13 12 11 10 9 cks0 cks2 dif pdn sclk mclk lr ck sd to a k5358b figure 6. ground layout note: - vss1 and vss2 must be connected to the same analog ground plane.
[ak5358b] ms1155-e-00 2010/02 - 16 - 1. grounding and power supply decoupling the ak5358b requires careful attention to power supply a nd grounding arrangements. alternatively if va and vd are supplied separately, the power up sequence is not critical. vss1 and vss2 of the ak5358b must be connected to analog ground plane. system analog ground and digital ground should be connected together near to where the supplies are brought onto the printed circuit board. decoupling capacitors should be as near to the ak5358a as possible, with the small value ceramic capac itor being the nearest. 2. voltage reference the voltage input to va sets the analog input range. vcom are 50%va and normally connected to vss1 with a 0.1 f ceramic capacitor. a capacitor 2.2 f is attached to vcom pin. no load current may be drawn from these pins. all signals, especially clocks, should be kept away from the vcom pin in order to avoid unwanted coupling into the ak5358b. 3. analog inputs the adc inputs are single-ended and internally biased to the common voltage (50%va) with 20k (typ@fs=48khz) resistance. the input signal range scales with the supply vo ltage and nominally 0.6xva vpp (typ). the adc output data format is 2?s complement. the inte rnal hpf removes the dc offset. the ak5358b samples the analog inputs at 64fs (@fs=48khz). the digital filter re jects noise above the stop band except for multiples of 64fs. the ak5358b incl udes an anti-aliasing filter (rc filter) to attenuate a noise around 64fs.
[ak5358b] ms1155-e-00 2010/02 - 17 - package 0-10 detail a seating plane 0.10 0.17 0.05 0.22 0.1 0.65 *5.0 0.1 1.1 (max) a 1 8 9 16 16pin tssop (unit: mm) *4.4 0.1 6.4 0.2 0.5 0.2 0.1 0.1 note: dimension "*" does not include mold flash. 0.13 m material & lead finish package molding compound: epoxy, halogen (bromine and chlorine) free lead frame material: cu lead frame surface treatme nt: solder (pb free) plate
[ak5358b] ms1155-e-00 2010/02 - 18 - marking akm 5358bet xxyyy 1) pin #1 indication 2) date code: xxyyy (5 digits) xx: lot# yyy: date code 3) marketing code: 5358bet date (yy/mm/dd) revision reason page contents 10/02/09 00 first edition revision history
[ak5358b] ms1155-e-00 2010/02 - 19 - important notice z these products and their specifications are subject to change without notice. when you consider any use or application of these produc ts, please make inquiries the sales office of asahi kasei microdevices corporation (akm) or authorized distributors as to current status of the products. z akm assumes no liability for infringement of any patent, intellectual property, or other rights in the application or use of any information contained herein. z any export of these products, or devices or systems containi ng them, may require an export license or other official approval under the law and regulations of the country of e xport pertaining to customs and tariffs, currency exchange, or strategic materials. z akm products are neither intended nor aut horized for use as critical components note1) in any safety, life support, or other hazard related device or system note2) , and akm assumes no responsibility fo r such use, except for the use approved with the express written consent by representative director of akm. as used here: note1) a critical component is one whose failure to func tion or perform may reasonably be expected to result, whether directly or indirectly, in the loss of the safety or effectiveness of the device or system containing it, and which must therefore meet very high standards of performance and reliability. note2) a hazard related device or syst em is one designed or intended for lif e support or maintenance of safety or for applications in medicine, aeros pace, nuclear energy, or other fields, in which its failure to function or perform may reasonably be expected to result in loss of life or in significant injury or damage to person or property. z it is the responsibility of the buyer or distributor of akm pr oducts, who distributes, dis poses of, or otherwise places the product with a third party, to notify such third party in advance of the above content and conditions, and the buyer or distributor agrees to assume any and a ll responsibility and liability fo r and hold akm harmless from any and all claims arising from the use of said product in the absence of such notification.

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